The UT54LVDS032LV/E quad CMOS differential line receiver with cold sparing on all pins designed for applications requiring ultra-low power dissipation and high data rates.
The quad receiver supports data rates up to 400.0Mbps utilizing Low Voltage Differential Signaling (LVDs) technology. The UT54LVDS032LV/E and companion quad line driver UT54LVDS031LV provide new alternatives to high power pseudo-ECL devices for high-speed point-to-point interface applications.
- Features:
- Quad Receiver
- >400.0 Mbps (200 MHz) switching rates
- ±340mV nominal differential signaling
- 3.3 V power supply
- TTL compatible inputs
- Cold sparing all pins
- Ultra-low power CMOS technology
- 1.9ns maximum, propagation delay
- 200ps maximum, differential skew
- Compatible with ANSI/TIA/EIA 644-1996 LVDS Standard
- Applications:
- LVDS Communication Systems
- Microprocessor and FPGA LVDS driver protection
- Operational Environment:
- Temperature Range: -55°C to +125°C
- Total Ionizing Dose: 1 Mrad (Si)
- SEL Immune: ≤100 MeV-cm2/mg
- Physical:
- 16-Lead Flatpack
- 50-mil Pitch
- Power:
- 1.25W (Maximum)
- Flight Grade:
- QML-Q, QML-V
- Export Control Classification Number (ECCN):
- 9A515.e.1
- SMD Number:
- 5962-98652
ADDITIONAL SPECIFICATIONS
Datasheet
Application Notes
App-Note-UT54LVDS_UT200SpW_FaultPropagation.pdf
App-Note-LVDS-33V-5V-Compatibility.pdf
App-Note-LVDS-ColdSpareFunctionality.pdf
App-Note-LVDS-HBM-ESD-Ratings.pdf
App-Note-LVDS-LVDM-Compatibility.pdf
App-Note-LVDS-FailsafeBiasing.pdf
App-Note-LVDS-ReceiverInputThresholds.pdf
App-Note-LVDS-PowerDissipation.pdf
App-Note-LVDS-PropagationDelays.pdf
App-Note-LVDS-TheoryOfOperation.pdf
IBIS Model
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