Deserializers

UT54LVDS218

Overview
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CAES UT54LVDS218 LVDS Deserialize

The UT54LVDS218 Deserializer converts the three Low Voltage Differential Signaling (LVDS) data streams into 21 bits of CMOS/TTL data.

At a clock frequency of 75MHz, a data rate of 525Mbps per LVDS data channel is supported, and a data throughput of 1.575Gbps.

All pins support Cold Sparing and the UT54LVDS218 Serializer allows the use of wide, high speed TTL interfaces while reducing overall EMI and cable size.

Key Tech Specs
  • Features:
  • LVDS to CMOS/TTL Deserializer
  • 15 to 75MHz shift clock support
  • 50% duty cycle on receiver output clock
  • Low power consumption
  • Cold sparing all pins
  • +1V common mode range (around +1.2V)
  • Narrow bus reduces cable size and cost
  • Up to 1.575 Gbps throughput
  • Up to 197 Megabytes/sec bandwidth
  • 325 mV (typ) swing LVDS devices for low EMI
  • PLL requires no external components
  • Rising edge strobe
  • Compatible with ANSI/TIA/EIA 644-1996 LVDS Standard
  • Applications:
  • LVDS Communication Systems
  • Microprocessor and FPGA LVDS driver protection
  • Operational Environment:
  • Temperature Range: -55°C to +125°C
  • Total Ionizing Dose: 1 Mrad (Si)
  • SEL Immune: ≤100 MeV-cm2/mg
  • Physical:
  • 48-Lead Flatpack
  • 25-mil Pitch
  • Power:
  • 1.25W (Maximum) 
  • Flight Grade:
  • QML-Q, QML-V
  • Export Control Classification Number (ECCN):
  • 9A515.e.2
  • SMD Number:
  • 5962-01535

ADDITIONAL SPECIFICATIONS

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