The UT8ER1M32 is a 32Mb, radiation hardened by design, high performance CMOS static RAM multichip module (MCM) that is functionally compatible with traditional 1Mx32 SRAM devices. Autonomous (master) and demanded (slave) scrubbing continues while deselected.
The device has a power-down feature that reduces power consumption by more than 90% when deselected, offered in a single package solution, and has superior SEU performance. Ideal for code execution in high performance microprocessors, microcontrollers and FPGAs.
- 32Mb, 1M x 32
- Asynchronous Interface
- Embedded EDAC – Master or Slave versions
- 20ns Read, 10ns Write Access Time
- Functionally compatible with traditional 1M x 32 SRAM devices
- CMOS compatible input and output levels
- Three-state bidirectional data bus
- Supply Voltage: +2.3V to +3.6V (Supply), +1.7V to +2.0V (Core)
- Microprocessors, microcontrollers, FPGAs
- Operational Environment:
- Temperature Range: -55°C to +105°C
- Total Ionizing Dose: <100 krad (Si)
- SEL Immune: ≤110 MeV-cm2/mg
- SEU Rate: <8.1 x E-16 errors/bit-day
- 132-Pin Side-Brazed Dual Cavity Ceramic Quad Flatpack
- Flight Grade:
- QML-Q, QML-Q+, QML-V
- Export Control Classification Number (ECCN):
- SMD Number:
During a test program review, it was discovered that input leakage was not measured on input pin /Scrub for all slave stacked SRAMs. This issue covers only slave devices and not master devices. No devices have failed at the customer and is considered a low risk.
Group D Seam Seal failure of microcircuit, memory, digital, CMOS, radiation-hardened, dual-voltage SRAM, Multichip Module
UT8ER1M32S test escape. Whole block of the test program found to be commented out
Changes to package outline, VIL/VIH, and absolute maximum ratings.
An internal review determined Total Ionizing Dose (TID) testing bias circuit was limiting current when performing radiation testing to 100 krad(Si) per MIL-STD-883, M1019, Condition A. As a result of this finding, samples from previously delivered wafer
Product Information Notice is to inform the industry about the CAES SRAMs low power read architecture
Corrected and New AC parameters for EDAC register access
SEE & Package drawing clarification
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